#pragma once

#include "asm/assembler.h"
#include "utility/bitfield.h"

namespace l8
{

// CPU Registers.
//
// 1) We would prefer to use an enum, but enum values are assignment-
// compatible with int, which has caused code-generation bugs.
//
// 2) We would prefer to use a class instead of a struct but we don't like
// the register initialization to depend on the particular initialization
// order (which appears to be different on OS X, Linux, and Windows for the
// installed versions of C++ we tried). Using a struct permits C-style
// "initialization". Also, the Register objects cannot be const as this
// forces initialization stubs in MSVC, making us dependent on initialization
// order.
//
// 3) By not using an enum, we are possibly preventing the compiler from
// doing certain constant folds, which may significantly reduce the
// code generated for some assembly instructions (because they boil down
// to a few constants). If this is a problem, we could change the code
// such that we use an enum in optimized mode, and the struct in debug
// mode. This way we get the compile-time error checking in debug mode
// and best performance in optimized code.
//
struct Register
{
    bool is_valid() const  { return 0 <= code_ && code_ < 8; }
    bool is(Register reg) const  { return code_ == reg.code_; }

    // eax, ebx, ecx and edx are byte registers, the rest are not.
    bool is_byte_register() const  { return code_ <= 3; }

    int code() const
    {
        ASSERT(is_valid());
        return code_;
    }

    int bit() const
    {
        ASSERT(is_valid());
        return 1 << code_;
    }

    // (unfortunately we can't make this private in a struct)
    int code_;
};

const Register eax = { 0 };
const Register ecx = { 1 };
const Register edx = { 2 };
const Register ebx = { 3 };
const Register esp = { 4 };
const Register ebp = { 5 };
const Register esi = { 6 };
const Register edi = { 7 };
const Register no_reg = { -1 };

struct XMMRegister
{
    bool is_valid() const
    {
        return 0 <= code_ && code_ < 2;
    }

    int code() const
    {
        ASSERT(is_valid());
        return code_;
    }

    int code_;
};

const XMMRegister xmm0 = { 0 };
const XMMRegister xmm1 = { 1 };
const XMMRegister xmm2 = { 2 };
const XMMRegister xmm3 = { 3 };
const XMMRegister xmm4 = { 4 };
const XMMRegister xmm5 = { 5 };
const XMMRegister xmm6 = { 6 };
const XMMRegister xmm7 = { 7 };

enum Condition
{
    // any value < 0 is considered no_condition
    no_condition    = -1,

    overflow        =  0,
    no_overflow     =  1,
    below           =  2,
    above_equal     =  3,
    equal           =  4,
    not_equal       =  5,
    below_equal     =  6,
    above           =  7,
    negative        =  8,
    positive        =  9,
    parity_even     = 10,
    parity_odd      = 11,
    less            = 12,
    greater_equal   = 13,
    less_equal      = 14,
    greater         = 15,

    // aliases
    carry           = below,
    not_carry       = above_equal,
    zero            = equal,
    not_zero        = not_equal,
    sign            = negative,
    not_sign        = positive
};

// Returns the equivalent of !cc.
// Negation of the default no_condition (-1) results in a non-default
// no_condition value (-2). As long as tests for no_condition check
// for condition < 0, this will work as expected.
inline Condition NegateCondition(Condition cc);

// Corresponds to transposing the operands of a comparison.
inline Condition ReverseCondition(Condition cc)
{
    switch (cc)
    {
        case below:
            return above;
        case above:
            return below;
        case above_equal:
            return below_equal;
        case below_equal:
            return above_equal;
        case less:
            return greater;
        case greater:
            return less;
        case greater_equal:
            return less_equal;
        case less_equal:
            return greater_equal;
        default:
            return cc;
    };
}

enum Hint
{
    no_hint = 0,
    not_taken = 0x2e,
    taken = 0x3e
};

// The result of negating a hint is as if the corresponding condition
// were negated by NegateCondition.  That is, no_hint is mapped to
// itself and not_taken and taken are mapped to each other.
static inline Hint NegateHint(Hint hint)
{
    return (hint == no_hint)
            ? no_hint
            : ((hint == not_taken) ? taken : not_taken);
}


// -----------------------------------------------------------------------------
// Machine instruction Operands

enum ScaleFactor {
  times_1 = 0,
  times_2 = 1,
  times_4 = 2,
  times_8 = 3,
  times_pointer_size = times_4,
  times_half_pointer_size = times_2
};

class Operand
{
public:
    // reg
    explicit Operand(Register reg);

    // [disp/r]
    explicit Operand(int32_t disp, RelocInfo::Mode rmode);
    // disp only must always be relocated

    // [base + disp/r]
    explicit Operand(Register base, int32_t disp,
                     RelocInfo::Mode rmode = RelocInfo::NONE);

    // [base + index*scale + disp/r]
    explicit Operand(Register base, Register index, ScaleFactor scale, int32_t disp,
                     RelocInfo::Mode rmode = RelocInfo::NONE);

    // [index*scale + disp/r]
    explicit Operand(Register index,
        ScaleFactor scale,
        int32_t disp,
        RelocInfo::Mode rmode = RelocInfo::NONE);

    static Operand StaticVariable(const ExternalReference& ext)
    {
        return Operand(reinterpret_cast<int32_t>(ext.address()),
                       RelocInfo::EXTERNAL_REFERENCE);
    }

    static Operand StaticArray(Register index,
                               ScaleFactor scale,
                               const ExternalReference& arr)
    {
        return Operand(index, scale, reinterpret_cast<int32_t>(arr.address()),
                       RelocInfo::EXTERNAL_REFERENCE);
    }

    // Returns true if this Operand is a wrapper for the specified register.
    bool is_reg(Register reg) const;

private:
    byte buf_[6];
    // The number of bytes in buf_.
    unsigned int len_;
    // Only valid if len_ > 4.
    RelocInfo::Mode rmode_;

    // Set the ModRM byte without an encoded 'reg' register. The
    // register is encoded later as part of the emit_operand operation.
    inline void set_modrm(int mod, Register rm);

    inline void set_sib(ScaleFactor scale, Register index, Register base);
    inline void set_disp8(int8_t disp);
    inline void set_dispr(int32_t disp, RelocInfo::Mode rmode);

    friend class Assembler;
};


// -----------------------------------------------------------------------------
// A Displacement describes the 32bit immediate field of an instruction which
// may be used together with a Label in order to refer to a yet unknown code
// position. Displacements stored in the instruction stream are used to describe
// the instruction and to chain a list of instructions using the same Label.
// A Displacement contains 2 different fields:
//
// next field: position of next displacement in the chain (0 = end of list)
// type field: instruction type
//
// A next value of null (0) indicates the end of a chain (note that there can
// be no displacement at position zero, because there is always at least one
// instruction byte before the displacement).
//
// Displacement _data field layout
//
// |31.....2|1......0|
// [  next  |  type  |

class Displacement
{
public:
    enum Type
    {
        UNCONDITIONAL_JUMP,
        CODE_RELATIVE,
        OTHER
    };

    int data() const
    { return data_; }

    Type type() const
    { return TypeField::decode(data_); }

    void next(Label* label) const
    {
        int n = NextField::decode(data_);
        n > 0 ? label->link_to(n) : label->Unuse();
    }

    void link_to(Label* label)
    { init(label, type()); }

    explicit Displacement(int data)
    { data_ = data; }

    Displacement(Label* label, Type type)
    { init(label, type); }

    void print()
    {
#if 0
        PrintF("%s (%x) ", (type() == UNCONDITIONAL_JUMP ? "jmp" : "[other]"),
               NextField::decode(data_));
#else
        ASSERT(!"not impl");
#endif
    }

private:

    int     data_;

    class TypeField: public BitField<Type, 0, 2> {};
    class NextField: public BitField<int,  2, 32-2> {};

    void init(Label* label, Type type);
};


// -----------------------------------------------------------------------------
// CpuFeatures keeps track of which features are supported by the target CPU.
// Supported features must be enabled by a Scope before use.
// Example:
//   if (CpuFeatures::IsSupported(SSE2)) {
//     CpuFeatures::Scope fscope(SSE2);
//     // Generate SSE2 floating point code.
//   } else {
//     // Generate standard x87 floating point code.
//   }
class CpuFeatures : public AllStatic
{
public:
    // Feature flags bit positions. They are mostly based on the CPUID spec.
    // (We assign CPUID itself to one of the currently reserved bits --
    // feel free to change this if needed.)
    enum Feature { SSE3 = 32, SSE2 = 26, CMOV = 15, RDTSC = 4, CPUID = 10 };

    // Detect features of the target CPU. Set safe defaults if the serializer
    // is enabled (snapshots must be portable).
    static void Probe();

    // Check whether a feature is supported by the target CPU.
    static bool IsSupported(Feature f)
    {
        return (supported_ & (static_cast<uint64_t>(1) << f)) != 0;
    }

    // Check whether a feature is currently enabled.
    static bool IsEnabled(Feature f)
    {
        return (enabled_ & (static_cast<uint64_t>(1) << f)) != 0;
    }

    // Enable a specified feature within a scope.
    class Scope BASE_EMBEDDED
    {
#ifdef DEBUG
    public:
        explicit Scope(Feature f)
        {
            ASSERT(CpuFeatures::IsSupported(f));
            old_enabled_ = CpuFeatures::enabled_;
            CpuFeatures::enabled_ |= (static_cast<uint64_t>(1) << f);
        }

        ~Scope()
        { CpuFeatures::enabled_ = old_enabled_; }
    private:
        uint64_t old_enabled_;
#else
    public:
        explicit Scope(Feature f) {}
#endif
    };
private:
    static uint64_t supported_;
    static uint64_t enabled_;
};


// -----------------------------------------------------------------------------
// Machine instruction Immediates

class Immediate
{
public:
    inline explicit Immediate(int x);
    inline explicit Immediate(const char* s);
    inline explicit Immediate(const ExternalReference& ext);
#if 0
    inline explicit Immediate(Handle<Object> handle);
    inline explicit Immediate(Smi* value);
#endif

    static Immediate CodeRelativeOffset(Label* label)
    {
        return Immediate(label);
    }

    bool is_zero() const
    { return x_ == 0 && rmode_ == RelocInfo::NONE; }

    bool is_int8() const
    {
        return -128 <= x_ && x_ < 128 && rmode_ == RelocInfo::NONE;
    }

    bool is_int16() const
    {
        return -32768 <= x_ && x_ < 32768 && rmode_ == RelocInfo::NONE;
    }

    int x() const
    { return x_; }

    RelocInfo::Mode rmode() const
    { return rmode_; }

private:
    inline explicit Immediate(Label* value);

    int x_;
    RelocInfo::Mode rmode_;
};


// -----------------------------------------------------------------------------
// ia32 assembler
class Assembler
{
public:
    Assembler(void * buffer, size_t size);

    ~Assembler();

    // GetCode emits any pending (non-emitted) code and fills the descriptor
    // desc. GetCode() is idempotent; it returns the same result if no other
    // Assembler functions are invoked in between GetCode() calls.
    void GetCode(CodeDesc* desc);

    // We check before assembling an instruction that there is sufficient
    // space to write an instruction and its relocation information.
    // The relocation writer's position must be kGap bytes above the end of
    // the generated instructions. This leaves enough space for the
    // longest possible ia32 instruction, 15 bytes, and the longest possible
    // relocation information encoding, RelocInfoWriter::kMaxLength == 16.
    // (There is a 15 byte limit on ia32 instruction length that rules out some
    // otherwise valid instructions.)
    // This allows for a single, fast space check per instruction.
    static const int kGap = 32;

    // generic interface functions
    int pc_offset() const  { return pc_ - buffer_; }

    // Check if there is less than kGap bytes available in the buffer.
    // If this is the case, we need to grow the buffer before emitting
    // an instruction or relocation information.
    inline bool overflow() const
    { return pc_ >= reloc_info_writer_.pos() - kGap; }

    // code emission
    void GrowBuffer();

    void emit(uint32_t x);

#if 0
    void emit(Handle<Object> handle);
#endif

    void emit(uint32_t x, RelocInfo::Mode rmode);
    void emit(const Immediate& x);
    void emit_w(const Immediate& x);

    // Emit the code-object-relative offset of the label's position
    void emit_code_relative_offset(Label* label);

    // instruction generation
    void emit_arith_b(int op1, int op2, Register dst, int imm8);

    // Emit a basic arithmetic instruction (i.e. first byte of the family is 0x81)
    // with a given destination expression and an immediate operand.  It attempts
    // to use the shortest encoding possible.
    // sel specifies the /n in the modrm byte (see the Intel PRM).
    void emit_arith(int sel, Operand dst, const Immediate& x);

    void emit_operand(Register reg, const Operand& adr);

    void emit_farith(int b1, int b2, int i);

    // labels
    void print(Label* L);
    void bind_to(Label* L, int pos);
    void link_to(Label* L, Label* appendix);

    // displacements
    Displacement disp_at(Label* L);
    void disp_at_put(Label* L, Displacement disp);
    void emit_disp(Label* L, Displacement::Type type);


    // record reloc info for current pc_
    void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);


    // Get the number of bytes available in the buffer.
    inline int available_space() const
    { return reloc_info_writer_.pos() - pc_; }

    // Avoid overflows for displacements etc.
    static const int kMaximalBufferSize = 512*MB;
    static const int kMinimalBufferSize = 4*KB;

#if 1
    // ---------------------------------------------------------------------------
    // Code generation
    //
    // - function names correspond one-to-one to ia32 instruction mnemonics
    // - unless specified otherwise, instructions operate on 32bit operands
    // - instructions on 8bit (byte) operands/registers have a trailing '_b'
    // - instructions on 16bit (word) operands/registers have a trailing '_w'
    // - naming conflicts with C++ keywords are resolved via a trailing '_'

    // NOTE ON INTERFACE: Currently, the interface is not very consistent
    // in the sense that some operations (e.g. mov()) can be called in more
    // the one way to generate the same instruction: The Register argument
    // can in some cases be replaced with an Operand(Register) argument.
    // This should be cleaned up and made more orthogonal. The questions
    // is: should we always use Operands instead of Registers where an
    // Operand is possible, or should we have a Register (overloaded) form
    // instead? We must be careful to make sure that the selected instruction
    // is obvious from the parameters to avoid hard-to-find code generation
    // bugs.

    // Insert the smallest number of nop instructions
    // possible to align the pc offset to a multiple
    // of m. m must be a power of 2.
    void Align(int m);

    // Stack
    void pushad();
    void popad();

    void pushfd();
    void popfd();

    void push(const Immediate& x);
    void push(Register src);
    void push(const Operand& src);
    void push(Label* label, RelocInfo::Mode relocation_mode);

    void pop(Register dst);
    void pop(const Operand& dst);

    void enter(const Immediate& size);
    void leave();

    // Moves
    void mov_b(Register dst, const Operand& src);
    void mov_b(const Operand& dst, int8_t imm8);
    void mov_b(const Operand& dst, Register src);

    void mov_w(Register dst, const Operand& src);
    void mov_w(const Operand& dst, Register src);

    void mov(Register dst, int32_t imm32);
    void mov(Register dst, const Immediate& x);

#if 0
    void mov(Register dst, Handle<Object> handle);
#endif

    void mov(Register dst, const Operand& src);
    void mov(Register dst, Register src);
    void mov(const Operand& dst, const Immediate& x);

#if 0
    void mov(const Operand& dst, Handle<Object> handle);
#endif

    void mov(const Operand& dst, Register src);

    void movsx_b(Register dst, const Operand& src);

    void movsx_w(Register dst, const Operand& src);

    void movzx_b(Register dst, const Operand& src);

    void movzx_w(Register dst, const Operand& src);

    // Conditional moves
    void cmov(Condition cc, Register dst, int32_t imm32);

#if 0
    void cmov(Condition cc, Register dst, Handle<Object> handle);
#endif

    void cmov(Condition cc, Register dst, const Operand& src);

    // Exchange two registers
    void xchg(Register dst, Register src);

    // Arithmetics
    void adc(Register dst, int32_t imm32);
    void adc(Register dst, const Operand& src);

    void add(Register dst, const Operand& src);
    void add(const Operand& dst, const Immediate& x);

    void and_(Register dst, int32_t imm32);
    void and_(Register dst, const Operand& src);
    void and_(const Operand& src, Register dst);
    void and_(const Operand& dst, const Immediate& x);

    void cmpb(const Operand& op, int8_t imm8);
    void cmpb_al(const Operand& op);
    void cmpw_ax(const Operand& op);
    void cmpw(const Operand& op, Immediate imm16);
    void cmp(Register reg, int32_t imm32);

#if 0
    void cmp(Register reg, Handle<Object> handle);
#endif

    void cmp(Register reg, const Operand& op);
    void cmp(const Operand& op, const Immediate& imm);

    void dec_b(Register dst);

    void dec(Register dst);
    void dec(const Operand& dst);

    void cdq();

    void idiv(Register src);

    // Signed multiply instructions.
    void imul(Register src);                               // edx:eax = eax * src.
    void imul(Register dst, const Operand& src);           // dst = dst * src.
    void imul(Register dst, Register src, int32_t imm32);  // dst = src * imm32.

    void inc(Register dst);
    void inc(const Operand& dst);

    void lea(Register dst, const Operand& src);

    // Unsigned multiply instruction.
    void mul(Register src);                                // edx:eax = eax * reg.

    void neg(Register dst);

    void not_(Register dst);

    void or_(Register dst, int32_t imm32);
    void or_(Register dst, const Operand& src);
    void or_(const Operand& dst, Register src);
    void or_(const Operand& dst, const Immediate& x);

    void rcl(Register dst, uint8_t imm8);

    void sar(Register dst, uint8_t imm8);
    void sar(Register dst);

    void sbb(Register dst, const Operand& src);

    void shld(Register dst, const Operand& src);

    void shl(Register dst, uint8_t imm8);
    void shl(Register dst);

    void shrd(Register dst, const Operand& src);

    void shr(Register dst, uint8_t imm8);
    void shr(Register dst);
    void shr_cl(Register dst);

    void sub(const Operand& dst, const Immediate& x);
    void sub(Register dst, const Operand& src);
    void sub(const Operand& dst, Register src);

    void test(Register reg, const Immediate& imm);
    void test(Register reg, const Operand& op);
    void test(const Operand& op, const Immediate& imm);

    void xor_(Register dst, int32_t imm32);
    void xor_(Register dst, const Operand& src);
    void xor_(const Operand& src, Register dst);
    void xor_(const Operand& dst, const Immediate& x);

    // Bit operations.
    void bt(const Operand& dst, Register src);
    void bts(const Operand& dst, Register src);

    // Miscellaneous
    void hlt();
    void int3();
    void nop();
    void rdtsc();
    void ret(int imm16);

    // Label operations & relative jumps (PPUM Appendix D)
    //
    // Takes a branch opcode (cc) and a label (L) and generates
    // either a backward branch or a forward branch and links it
    // to the label fixup chain. Usage:
    //
    // Label L;    // unbound label
    // j(cc, &L);  // forward branch to unbound label
    // bind(&L);   // bind label to the current pc
    // j(cc, &L);  // backward branch to bound label
    // bind(&L);   // illegal: a label may be bound only once
    //
    // Note: The same Label can be used for forward and backward branches
    // but it may be bound only once.

    void bind(Label* L);  // binds an unbound label L to the current code position

    // Calls
    void call(Label* L);
    void call(byte* entry, RelocInfo::Mode rmode);
    void call(const Operand& adr);

#if 0
    void call(Handle<Code> code, RelocInfo::Mode rmode);
#endif

    // Jumps
    void jmp(Label* L);  // unconditional jump to L
    void jmp(byte* entry, RelocInfo::Mode rmode);
    void jmp(const Operand& adr);

#if 0
    void jmp(Handle<Code> code, RelocInfo::Mode rmode);
#endif

    // Conditional jumps
    void j(Condition cc, Label* L, Hint hint = no_hint);
    void j(Condition cc, byte* entry, RelocInfo::Mode rmode, Hint hint = no_hint);

#if 0
    void j(Condition cc, Handle<Code> code, Hint hint = no_hint);
#endif

    // Floating-point operations
    void fld(int i);

    void fld1();
    void fldz();

    void fld_s(const Operand& adr);
    void fld_d(const Operand& adr);

    void fstp_s(const Operand& adr);
    void fstp_d(const Operand& adr);

    void fild_s(const Operand& adr);
    void fild_d(const Operand& adr);

    void fist_s(const Operand& adr);

    void fistp_s(const Operand& adr);
    void fistp_d(const Operand& adr);

    void fisttp_s(const Operand& adr);

    void fabs();
    void fchs();
    void fcos();
    void fsin();

    void fadd(int i);
    void fsub(int i);
    void fmul(int i);
    void fdiv(int i);

    void fisub_s(const Operand& adr);

    void faddp(int i = 1);
    void fsubp(int i = 1);
    void fsubrp(int i = 1);
    void fmulp(int i = 1);
    void fdivp(int i = 1);
    void fprem();
    void fprem1();

    void fxch(int i = 1);
    void fincstp();
    void ffree(int i = 0);

    void ftst();
    void fucomp(int i);
    void fucompp();
    void fcompp();
    void fnstsw_ax();
    void fwait();
    void fnclex();

    void frndint();

    void sahf();
    void setcc(Condition cc, Register reg);

    void cpuid();

    // SSE2 instructions
    void cvttss2si(Register dst, const Operand& src);
    void cvttsd2si(Register dst, const Operand& src);

    void cvtsi2sd(XMMRegister dst, const Operand& src);

    void addsd(XMMRegister dst, XMMRegister src);
    void subsd(XMMRegister dst, XMMRegister src);
    void mulsd(XMMRegister dst, XMMRegister src);
    void divsd(XMMRegister dst, XMMRegister src);

    // Use either movsd or movlpd.
    void movdbl(XMMRegister dst, const Operand& src);
    void movdbl(const Operand& dst, XMMRegister src);
#endif

protected:
    void movsd(XMMRegister dst, const Operand& src);
    void movsd(const Operand& dst, XMMRegister src);

    void emit_sse_operand(XMMRegister reg, const Operand& adr);
    void emit_sse_operand(XMMRegister dst, XMMRegister src);

private:
    DISALLOW_COPY_AND_ASSIGN(Assembler);

    byte* addr_at(int pos) const
    { return buffer_ + pos; }

    byte byte_at(int pos) const
    { return buffer_[pos]; }

    uint32_t long_at(int pos) const
    {
        return *reinterpret_cast<uint32_t*>(addr_at(pos));
    }

    void long_at_put(int pos, uint32_t x)
    {
        *reinterpret_cast<uint32_t*>(addr_at(pos)) = x;
    }


    // Code buffer:
    // The buffer into which code and relocation info are generated.
    byte*           buffer_;
    int             buffer_size_;

    // True if the assembler owns the buffer, false if buffer is external.
    bool            own_buffer_;
    // A previously allocated buffer of kMinimalBufferSize bytes, or NULL.
    static byte*    spare_buffer_;

    // code generation
    byte*           pc_;  // the program counter; moves forward
    RelocInfoWriter reloc_info_writer_;

    // push-pop elimination
    byte*           last_pc_;

    // source position information
    int             current_statement_position_;
    int             current_position_;
    int             written_statement_position_;
    int             written_position_;
};

// Helper class that ensures that there is enough space for generating
// instructions and relocation information.  The constructor makes
// sure that there is enough space and (in debug mode) the destructor
// checks that we did not generate too much.
class EnsureSpace
{
public:
    explicit EnsureSpace(Assembler* assembler)
            : assembler_(assembler)
    {
        if (assembler_->overflow())
        {
            assembler_->GrowBuffer();
        }

#ifdef DEBUG
        space_before_ = assembler_->available_space();
#endif
    }

#ifdef DEBUG
    ~EnsureSpace()
    {
        int bytes_generated = space_before_ - assembler_->available_space();
        ASSERT(bytes_generated < assembler_->kGap);
    }
#endif

private:
    Assembler* assembler_;

#ifdef DEBUG
    int space_before_;
#endif
};

} // namespace l8

